View MAX1444EHJT_4754088.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the max1444 10-bit, 3v analog-to-digital converter (adc) features a pipelined 10-stage adc architecture with fully differential wideband track-and-hold (t/h) input and digital error correction incorporating a fully differential signal path. this adc is optimized for low- power, high dynamic performance applications in imaging and digital communications. the max1444 operates from a single 2.7v to 3.6v supply, consuming only 57mw while delivering a 59.5db signal-to-noise ratio (snr) at a 20mhz input frequency. the fully differ- ential input stage has a 400mhz -3db bandwidth and may be operated with single-ended inputs. in addition to low operating power, the max1444 features a 5? power-down mode for idle periods. an internal 2.048v precision bandgap reference is used to set the adc full-scale range. a flexible refer- ence structure allows the user to supply a buffered, direct, or externally derived reference for applications requiring increased accuracy or a different input volt- age range. higher speed, pin-compatible versions of the max1444 are also available. please refer to the max1446 data sheet (60msps) and the max1448 data sheet (80msps). the max1444 has parallel, offset binary, cmos-com- patible three-state outputs that can be operated from 1.7v to 3.6v to allow flexible interfacing. the device is available in a 5x5mm 32-pin tqfp package and is specified over the extended industrial (-40? to +85?) temperature range. ________________________applications ultrasound imaging ccd imaging baseband and if digitization digital set-top boxes video digitizing applications features ? single 3.0v operation ? excellent dynamic performance 59.5db snr at f in = 20mhz 74dbc sfdr at f in = 20mhz ? low power 19ma (normal operation) 5a (shutdown mode) ? fully differential analog input ? wide 2v p-p differential input voltage range ? 400mhz -3db input bandwidth ? on-chip 2.048v precision bandgap reference ? cmos-compatible three-state outputs ? 32-pin tqfp package ? evaluation kit available max1444 10-bit, 40msps, 3.0v, low-power adc with internal reference ________________________________________________________________ maxim integrated products 1 max1444 tqfp top view 32 28 29 30 31 25 26 27 refin gnd refout d0 refp d1 d2 d3 10 13 15 14 16 11 12 9 v dd gnd v dd pd clk oe gnd d9 17 18 19 20 21 22 23 ognd 24 d4 t.p. ov dd d5 d6 d7 d8 2 3 4 5 6 7 8 gnd in- in+ gnd gnd v dd com 1 refn pin configuration 19-1745; rev 2; 4/04 evaluation kit available ordering information functional diagram appears at end of data sheet. part temp range pin-package max1444ehj -40 c to +85 c 32 tqfp for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
max1444 10-bit, 40msps, 3.0v, low-power adc with internal reference 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = 3v; ov dd = 2.7v; 0.1? and 1? capacitors from refp, refn, and com to gnd; v refin = 2.048v; refout connected to refin through a 10k ? resistor; v in = 2v p-p (differential with respect to com); c l = 10pf at digital outputs; f clk = 40mhz; t a = t min to t max , unless otherwise noted. +25? guaranteed by production test, < +25? guaranteed by design and characterization; typi- cal values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd , ov dd to gnd ...............................................-0.3v to +3.6v ognd to gnd.......................................................-0.3v to +0.3v in+, in- to gnd........................................................-0.3v to v dd refin, refout, refp, refn, and com to gnd........................-0.3v to (v dd + 0.3v) oe , pd, clk to gnd..................................-0.3v to (v dd + 0.3v) d9?0 to gnd.........................................-0.3v to (ov dd + 0.3v) continuous power dissipation (t a = +70?) 32-pin tqfp (derate 18.7mw/? above +70?).....1495.3mw operating temperature range ...........................-40? to +85? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units dc accuracy resolution 10 bits integral nonlinearity inl f in = 7.51mhz, t a +25? 0.6 1.9 lsb differential nonlinearity dnl f in = 7.51mhz, no missing codes guaranteed 0.4 1.0 lsb offset error < 0.1 1.7 % fs gain error t a +25? 0 2% fs analog input input differential range v diff differential or single-ended inputs 1.0 v common-mode voltage range v com v dd /2 0.5 v input resistance r in switched capacitor load 50 k ? input capacitance c in 5pf conversion rate maximum clock frequency f clk 40 mhz data latency 5.5 cycles dynamic characteristics (f clk = 40mhz, 4096-point fft) f in = 7.51mhz 57.5 59.5 f in = 19.91mhz 56.3 59.5 signal-to-noise ratio snr f in = 39.9mhz (note 1) 58.5 db f in = 7.51mhz 57 59.4 f in = 19.91mhz 56.1 59 signal-to-noise + distortion (up to 5th harmonic) sinad f in = 39.9mhz (note 1) 58.3 db f in = 7.51mhz 67 75 f in = 19.91mhz 66 74 spurious-free dynamic range sfdr f in = 39.9 mhz (note 1) 72.5 dbc
max1444 10-bit, 40msps, 3.0v, low-power adc with internal reference _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = 3v; ov dd = 2.7v; 0.1? and 1? capacitors from refp, refn, and com to gnd; v refin = 2.048v; refout connected to refin through a 10k ? resistor; v in = 2v p-p (differential with respect to com); c l = 10pf at digital outputs; f clk = 40mhz; t a = t min to t max , unless otherwise noted. +25? guaranteed by production test, < +25? guaranteed by design and characterization; typi- cal values are at t a = +25?.) parameter symbol conditions min typ max units f in = 7.51mhz -75 f in = 19.91mhz -74 third-harmonic distortion hd3 f in = 39.9mhz (note 1) -72.5 dbc two-tone intermodulation distortion imd f 1 = 11.5mhz at -6.5dbfs f 2 = 13.5mhz at -6.5dbfs (note 2) -76 dbc third-order intermodulation distortion im3 f 1 = 11.5mhz at -6.5dbfs f 2 = 13.5mhz at -6.5dbfs (note 2) -76 dbc f in = 7.51mhz -73.8 -65 f in = 19.91mhz -72.2 -65 total harmonic distortion (first 4 harmonics) thd f in = 39.9mhz (note 1) -70 dbc small-signal bandwidth input at -20dbfs, differential inputs 500 mhz full-power bandwidth fpbw input at -0.5dbfs, differential inputs 400 mhz aperture delay t ad 1ns aperture jitter t aj 2 ps rms overdrive recovery time for 1.5 full-scale input 2 ns differential gain 1% differential phase 0.25 degrees output noise in+ = in- = com 0.2 ls b rm s internal reference reference output voltage refout 2.048 1% v reference temperature coefficient tc ref 60 p p m/ c load regulation 1.25 mv/ma buffered external reference (v refin = 2.048v) refin input voltage v refin 2.048 v positive reference output voltage v refp 2.012 v negative reference output voltage v refn 0.988 v common-mode level v com v dd / 2 v differential reference output voltage range ? v ref ? v ref = v refp - v refn , t a +25? 0.98 1.024 1.07 v refin resistance r refin >50 m ?
max1444 10-bit, 40msps, 3.0v, low-power adc with internal reference 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units maximum refp, com source current i s ou rc e 5ma maximum refp, com sink current i sink -250 ? maximum refn source current i s ou rc e 250 ? maximum refn sink current i sink -5 ma unbuffered external reference (v refin = agnd, reference voltage applied to refp, refn, and com) refp, refn input resistance r refp , r refn measured between refp and com and refn and com 4k ? refp, refn, com input capacitance c in 15 pf differential reference input voltage range ? v ref ? v ref = v refp - v refn 1.024 10% v com input voltage range v com v dd / 2 10% v refp input voltage v refp v c om + ? v re f / 2 v refn input voltage v refn v com - ? v ref / 2 v digital inputs (clk, pd, oe ) clk 0.8 v dd input high threshold v ih pd, oe 0.8 v dd input low threshold v il pd, oe 0.2 electrical characteristics (continued) (v dd = 3v; ov dd = 2.7v; 0.1? and 1? capacitors from refp, refn, and com to gnd; v refin = 2.048v; refout connected to refin through a 10k ? resistor; v in = 2v p-p (differential with respect to com); c l = 10pf at digital outputs; f clk = 40mhz; t a = t min to t max , unless otherwise noted. +25? guaranteed by production test, < +25? guaranteed by design and characterization; typi- cal values are at t a = +25?.)
max1444 10-bit, 40msps, 3.0v, low-power adc with internal reference _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units input hysteresis v hyst 0.1 v i ih v ih = v dd = ov dd 5 input leakage i il v il = 0 5 ? input capacitance c in 5pf digital outputs (d9?0) output voltage low v ol i sink = 200 a 0.2 v output voltage high v oh i source = 200 a ov dd - 0.2 v three-state leakage current i leak oe = ov dd 10 ? three-state output capacitance c out oe = ov dd 5pf power requirements analog supply voltage v dd 2.7 3.0 3.6 v output supply voltage ov dd 1.7 3.0 3.6 v o p er ati ng , f i n = 19.91m h z at - 0.5d bfs 19 27 ma analog supply current i vdd s hutd ow n, cl ock i d l e, p d = o e = ov d d 415a o p er ati ng , f i n = 19.91m h z at - 0.5d bfs 4.5 ma output supply current i ovdd s hutd ow n, cl ock i d l e, p d = o e = ov d d 120a offset 0.1 mv/v power-supply rejection psrr gain 0.1 %/v timing characteristics clk rise to output data valid t do figure 6 (note 3) 5 8 ns oe fall to output enable t enable figure 5 10 ns oe rise to output disable t disable figure 5 15 ns clk pulse width high t ch figure 6, clock period 25ns 12.5 3.8 ns clk pulse width low t cl figure 6, clock period 25ns 12.5 3.8 ns wake-up time t wake (note 4) 1.7 ? electrical characteristics (continued) (v dd = 3v; ov dd = 2.7v; 0.1? and 1? capacitors from refp, refn, and com to gnd; v refin = 2.048v; refout connected to refin through a 10k ? resistor; v in = 2v p-p (differential with respect to com); c l = 10pf at digital outputs; f clk = 40mhz; t a = t min to t max , unless otherwise noted. +25? guaranteed by production test, < +25? guaranteed by design and characterization; typi- cal values are at t a = +25?.) note 1: snr, sinad, thd, sfdr, and hd3 are based on an analog input voltage of -0.5dbfs referenced to a 1.024v full-scale input voltage range. note 2: intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. this number i s 6db better if referenced to the two-tone envelope. note 3: digital outputs settle to v ih , v il . note 4: refin is driven externally. refp, com, and refn are left floating while powered down.
max1444-01 -100 -70 -80 -90 -50 -60 -10 -20 -30 -40 0 0246 810121 4161820 analog input frequency (mhz) amplitude (db) sinad = 59db snr = 59.3db thd = -71.6dbc sfdr = 73dbc fft plot (f in = 7.51mhz, 8192-point fft, differential input) 3rd harmonic 2nd harmonic max1444-02 -100 -70 -80 -90 -50 -60 -10 -20 -30 -40 0 0246 810121 4161820 analog input frequency (mhz) amplitude (db) sinad = 58.9db snr = 59.1db thd = -72.8dbc sfdr = 75.2dbc fft plot (f in = 19.91mhz, 8192-point fft, differential input) 3rd harmonic 2nd harmonic max1444-03 -100 -70 -80 -90 -50 -60 -10 -20 -30 -40 0 0510 15 20 25 fft plot (f in = 47mhz, 8192-point fft, differential input) analog input frequency (mhz) amplitude (db) sinad = 58.1db snr = 58.4db thd = -69.7dbc sfdr = 72.4dbc 3rd harmonic 2nd harmonic max1444-04 -100 -70 -80 -90 -50 -60 -10 -20 -30 -40 0 0246 810121 4161820 analog input frequency (mhz) amplitude (db) sinad = 59.7db snr = 60db thd = -71.8dbc sfdr = 75dbc fft plot (f in = 7.51mhz, 8192-point fft, single-ended input) 3rd harmonic 2nd harmonic max1444-05 -100 -70 -80 -90 -50 -60 -10 -20 -30 -40 0 0246 810121 4161820 analog input frequency (mhz) amplitude (db) sinad = 59.1db snr = 59.2db thd = -74.6dbc sfdr = 77.6dbc fft plot (f in = 19.91mhz, 8192-point fft, single-ended input) 3rd harmonic 2nd harmonic 6 1 100 1000 full-power input bandwidth vs. analog input frequency (single ended) -6 -8 -4 -2 0 2 4 max1444-06 analog input frequency (mhz) gain (db) 10 6 1 100 1000 small-signal input bandwidth vs. analog input frequency (single ended) -6 -8 -4 -2 0 2 4 max1444-07 analog input frequency (mhz) gain (db) 10 v in = 100mvp-p max1444-08 -100 -70 -80 -90 -50 -60 -10 -20 -30 -40 0 0510 15 20 25 analog input frequency (mhz) amplitude (db) two-tone intermodulation 8192-point imd (differential input) f 1 = 11.5mhz at -6.5db fs f 2 = 13.5mhz at -6.5db fs imd = -76dbc 80 40 110 100 spurious-free dynamic range vs. analog input frequency 50 45 max1444-09 analog input frequency (mhz) sfdr (dbc) 60 55 65 70 75 single ended differential max1444 10-bit, 40msps, 3.0v, low-power adc with internal reference 6 _______________________________________________________________________________________ t ypical operating characteristics (v dd = 3.0v, ov dd = 2.7v, internal reference, differential input at -0.5db fs, f clk = 40mhz, c l 10pf, t a = +25?, unless other- wise noted.)
62 54 110 100 56 55 max1444-10 analog input frequency (mhz) snr (db) 58 57 59 60 61 signal-to-noise ratio vs. analog input frequency single ended differential -45 -75 110 100 -70 max1444-11 analog input frequency (mhz) thd (dbc) -60 -65 -55 -50 total harmonic distortion vs. analog input frequency single ended differential 65 45 110 100 49 max1444-12 analog input frequency (mhz) sinad (db) 53 57 61 signal-to-noise + distortion vs. analog input frequency single ended differential 50 60 55 70 65 75 80 -15 -9 -12 -6 -3 0 spurious-free dynamic range vs. analog input power max1444-13 analog input power (db fs) sfdr (dbc) f in = 19.91mhz 40 50 45 55 60 65 -15 -9 -12 -6 -3 0 signal-to-noise ratio vs. analog input power max1444-14 analog input power (db fs) snr (db) f in = 19.91mhz -80 -70 -75 -60 -65 -55 -50 -15 -9 -12 -6 -3 0 total harmonic distortion vs. analog input power max1444-15 analog input power (db fs) thd (dbc) f in = 19.91mhz 40 50 45 55 60 65 -15 -9 -12 -6 -3 0 signal-to-noise + distortion vs. analog input power max1444-16 analog input power (db fs) sinad (db) f in = 19.91mhz 68 64 76 72 80 84 -40 10 -15 35 60 85 spurious-free dynamic range vs. temperature max1444-17 temperature ( c) sfdr (dbc) f in = 19.91mhz 54 50 62 58 66 70 -40 10 -15 35 60 85 signal-to-noise ratio vs. temperature max1444-18 temperature (?) snr (db) f in = 19.91mhz max1444 10-bit, 40msps, 3.0v, low-power adc with internal reference _______________________________________________________________________________________ 7 t ypical operating characteristics (continued) (v dd = 3.0v, ov dd = 2.7v, internal reference, differential input at -0.5db fs, f clk = 40mhz, c l 10pf, t a = +25?, unless other- wise noted.)
-76 -80 -68 -72 -64 -60 -40 10 -15 35 60 85 total harmonic distortion vs. temperature max1444-19 temperature ( c) thd (dbc) f in = 19.91mhz 54 50 62 58 66 70 -40 10 -15 35 60 85 signal-to-noise + distortion vs. temperature max1444-20 temperature ( c) sinad (db) f in = 19.91mhz -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0 400 200 600 800 1000 1200 integral nonlinearity vs. digital output code (best straight line) max1444-21 digital output code inl (lsb) 0 400 200 600 800 1000 1200 max1444-22 digital output code dnl (lsb) differential nonlinearity vs. digital output code -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 -0.03 -0.04 -0.05 0.01 0 -0.01 -0.02 0.03 0.02 0.05 0.04 -40 10 -15 35 60 85 max1444-23 temperature ( c) gain error (lsb) gain error vs. temperature, external reference (v refin = 2.048v) 2 0 6 4 8 10 -40 10 -15 35 60 85 max1444-24 temperature ( c) offset error (lsb) offset error vs. temperature, external reference (v refin = 2.048v) 16 14 20 18 22 24 -40 10 -15 35 60 85 max1444-26 temperature ( c) i vdd (ma) analog supply current vs. temperature 1 0 3 2 5 4 6 1.6 2.4 2.0 2.8 3.2 3.6 max1444-27 ov dd (v) i ovdd (ma) digital supply current vs. digital supply voltage f in = 7.51mhz 16 14 20 18 22 24 2.70 3.00 2.85 3.15 3.30 3.45 3.60 analog supply current vs. analog supply voltage max1444-25 v dd (v) i vdd (ma) max1444 10-bit, 40msps, 3.0v, low-power adc with internal reference 8 _______________________________________________________________________________________ t ypical operating characteristics (continued) (v dd = 3.0v, ov dd = 2.7v, internal reference, differential input at -0.5db fs, f clk = 40mhz, c l 10pf, t a = +25?, unless other- wise noted.)
1 0 3 2 4 5 -40 10 -15 35 60 85 max1444-28 temperature (?) i ovdd (ma) digital supply current vs. temperature f in = 7.51mhz 3.0 2.5 2.0 4.0 3.5 4.5 5.0 2.70 3.00 2.85 3.15 3.30 3.45 3.60 analog power-down current vs. analog power supply max1444-29 v dd (v) i vdd ( a) oe = ov dd , pd = v dd 2 0 6 4 8 10 1.2 1.8 2.4 3.0 3.6 digital power-down current vs. digital power supply max1444-30 ov dd (v) i ovdd ( a) pd = v dd , oe = ov dd 55 50 65 60 75 70 80 30 38 34 42 46 50 max1444-31 f clk (mhz) snr/sinad, thd/sfdr (db, dbc) snr/sinad, thd/sfdr vs. clock frequency (over-clocking) f in = 13.24mhz thd sfdr snr sinad 2.02 2.00 2.06 2.04 2.08 2.10 2.70 2.85 3.00 3.15 3.30 3.45 3.60 internal reference voltage vs. analog supply voltage max1444-32 v dd (v) v refout (v) 2.02 2.00 2.06 2.04 2.08 2.10 -40 10 -15 35 60 85 max1444-33 temperature (?) v refout (v) internal reference voltage vs. temperature 0 7000 21000 14000 28000 35000 42000 56000 49000 63000 70000 n-2 n-1 n n+1 n+2 0 869 64515 152 0 output noise histogram (dc input) max1444-34 digital output code counts max1444 10-bit, 40msps, 3.0v, low-power adc with internal reference _______________________________________________________________________________________ 9 t ypical operating characteristics (continued) (v dd = 3.0v, ov dd = 2.7v, internal reference, differential input at -0.5db fs, f clk = 40mhz, c l 10pf, t a = +25?, unless other- wise noted.)
max1444 10-bit, 40msps, 3.0v, low-power adc with internal reference 10 ______________________________________________________________________________________ pin description pin name function 1 refn lower reference. conversion range is (v refp - v refn ). bypass to gnd with a > 0.1 f capacitor. 2 com common-mode voltage output. bypass to gnd with a >0.1 f capacitor. 3, 9, 10 v dd analog supply voltage. bypass to gnd with a capacitor combination of 2.2 f in parallel with 0.1 f. 4, 5, 8, 11, 14, 30 gnd analog ground 6 in+ positive analog input. for single-ended operation, connect signal source to in+. 7 in- negative analog input. for single-ended operation, connect in- to com. 12 clk conversion clock input 13 pd power down input. high: power-down mode. low: normal operation. 15 oe output enable input. high: digital outputs disabled. low: digital outputs enabled. 16?0 d9?5 three-state digital outputs d9?5. d9 is the msb. 21 ov dd output driver supply voltage. bypass to gnd with a capacitor combination of 2.2 f in parallel with 0.1 f. 22 t.p. test point. do not connect. 23 ognd output driver ground 24?8 d4?0 three-state digital outputs d4?0. d0 is the lsb. 29 refout internal reference voltage output. may be connected to refin through a resistor or a resistor-divider. 31 refin reference input. v refin = 2 (v refp - v refn ). bypass to gnd with a >0.1 f capacitor. 32 refp upper reference. conversion range is (v refp - v refn ). bypass to gnd with a >0.1 f capacitor.
max1444 10-bit, 40msps, 3.0v, low-power adc with internal reference ______________________________________________________________________________________ 11 detailed description the max1444 uses a 10-stage, fully differential, pipelined architecture (figure 1) that allows for high- speed conversion while minimizing power consump- tion. each sample moves through a pipeline stage every half-clock cycle. counting the delay through the output latch, the clock-cycle latency is 5.5. a 1.5-bit (2-comparator) flash adc converts the held input voltage into a digital code. the following digital- to-analog converter (dac) converts the digitized result back into an analog voltage, which is then subtracted from the original held input signal. the resulting error signal is then multiplied by two, and the product is passed along to the next pipeline stage where the process is repeated until the signal has been processed by all 10 stages. each stage provides a 1-bit resolution. input track-and-hold circuit figure 2 displays a simplified functional diagram of the input track-and-hold (t/h) circuit in both track and hold mode. in track mode, switches s1, s2a, s2b, s4a, s4b, s5a, and s5b are closed. the fully differential circuit samples the input signal onto the two capacitors (c2a and c2b). switches s2a and s2b set the common mode for the amplifier input. the resulting differential voltage is held on c2a and c2b. switches s4a, s4b, s5a, s5b, s1, s2a, and s2b are then opened before s3a, s3b, and s4c are closed, connecting capacitors c1a and c1b to the amplifier output. this charges c1a and c1b to the same values originally held on c2a and c2b. this value is then presented to the first-stage quantizer and isolates the pipeline from the fast-chang- ing input. the wide-input-bandwidth t/h amplifier allows the max1444 to track and sample/hold analog inputs of high frequencies beyond nyquist. the analog inputs (in+ and in-) can be driven either differentially or single-ended. it is recommended to match the impedance of in+ and in- and set the common-mode voltage to midsupply (v dd /2) for optimum performance. analog input and reference configuration the max1444 full-scale range is determined by the internally generated voltage difference between refp (v dd /2 + v refin /4) and refn (v dd /2 - v refin /4). the adc? full-scale range is user-adjustable through the refin pin, which provides a high input impedance for this purpose. refout, refp, com (v dd /2), and refn are internally buffered, low-impedance outputs. t/h v out x2 flash adc dac 1.5 bits mdac 10 v in v in stage 1 stage 2 d9?0 v in = input voltage between in+ and in- (differential or single-ended) digital alignment logic stage 10 figure 1. pipelined architecture?tage blocks s3b s3a com s5b s5a in+ in- s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias internal bias com track track internal non-overlapping clock signals clk hold hold s2a s2b figure 2. internal t/h circuit
max1444 10-bit, 40msps, 3.0v, low-power adc with internal reference 12 ______________________________________________________________________________________ the max1444 provides three modes of reference oper- ation: ? nternal reference mode ? uffered external reference mode unbuffered external reference mode in internal reference mode, the internal reference out- put (refout) can be tied to the refin pin through a resistor (e.g., 10k ? ) or resistor-divider if an application requires a reduced full-scale range. for stability pur- poses, it is recommended to bypass refin with a >10nf capacitor to gnd. in buffered external reference mode, the reference vol- tage levels can be adjusted externally by applying a stable and accurate voltage at refin. in this mode, refout may be left open or connected to refin through a >10k ? resistor. in unbuffered external reference mode, refin is con- nected to gnd, thereby deactivating the on-chip buffers of refp, com, and refn. with their buffers shut down, these pins become high impedance inputs and can be driven by external reference sources. clock input (clk) the max1444 clk input accepts cmos-compatible clock signals. since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). in particular, sampling occurs on the falling edge of the clock signal, mandating this edge to provide lowest possible jitter. any significant aperture jitter would limit the snr per- formance of the adc as follows: snr = 20log (1 / 2 f in t aj ) where f in represents the analog input frequency, and t aj is the time of the aperture jitter. clock jitter is especially critical for undersampling applications. the clock input should always be consid- ered as an analog input and routed away from any ana- log input or other digital signal lines. the max1444 clock input operates with a voltage threshold set to v dd /2. clock inputs with a duty cycle other than 50% must meet the specifications for high and low periods as stated in the electrical character- istics . see figures 3a, 3b, 4a, and 4b for the relation- ship between spurious-free dynamic range (sfdr), signal-to-noise ratio (snr), total harmonic distortion (thd), or signal-to-noise plus distortion (sinad) versus clock duty cycle. output enable ( oe ), power down (pd), and output data (d0?9) all data outputs, d0 (lsb) through d9 (msb), are ttl/cmos-logic compatible. there is a 5.5 clock-cycle latency between any particular sample and its valid output data. the output coding is straight offset binary (table 1). with oe and pd (power down) high, the digi- tal output enters a high-impedance state. if oe is held low with pd high, the outputs are latched at the last value prior to the power down. the capacitive load on the digital outputs d0?9 should be kept as low as possible (<15pf) to avoid large digital currents that could feed back into the ana- log portion of the max1444, thus degrading its dynam- ic performance. the use of buffers on the adc? digital outputs can further isolate the digital outputs from heavy capacitive loads. figure 5 displays the timing relationship between out- put enable and data output valid as well as power- down/wake-up and data output valid. table 1. max1444 output code for differential inputs differential input voltage* differential input straight offset binary v ref 511/512 +full scale -1lsb 11 1111 1111 v ref 510/512 +full scale -2lsb 11 1111 1110 v ref 1/512 +1lsb 10 0000 0001 0 bipolar zero 10 0000 0000 - v ref 1/512 -1lsb 01 1111 1111 - v ref 511/512 negative full scale + 1lsb 00 0000 0001 - v ref 512/512 negative full scale 00 0000 0000 * v ref = v refp - v refn
max1444 10-bit, 40msps, 3.0v, low-power adc with internal reference ______________________________________________________________________________________ 13 60 65 80 75 70 85 90 20 40 30 50 60 70 clock duty cycle (%) sfdr (dbc) f in = 13.24mhz at-0.5db fs figure 3a. spurious-free dynamic range vs. clock duty cycle (differential input) 56 57 59 58 60 61 20 40 30 50 60 70 clock duty cycle (%) snr (db) f in = 13.24mhz at-0.5db fs figure 3b. signal-to-noise ratio vs. clock duty cycle (differential input) -80 -76 -68 -72 -64 -60 20 40 30 50 60 70 clock duty cycle (%) thd (dbc) f in = 13.24mhz at-0.5db fs figure 4a. total harmonic distortion vs. clock duty cycle (differential input) 61 60 59 58 57 20 40 30 50 60 70 clock duty cycle (%) sinad (db) f in = 13.24mhz at-0.5db fs figure 4b. signal-to-noise plus distortion vs. clock duty cycle (differential input) output data d9?0 oe t disable t enable high-z high-z valid data figure 5. output enable timing
max1444 10-bit, 40msps, 3.0v, low-power adc with internal reference 14 ______________________________________________________________________________________ n - 6 n n - 5 n + 1 n - 4 n + 2 n - 3 n + 3 n - 2 n + 4 n - 1 n + 5 n n + 6 n + 1 n + 7 5.5 clock-cycle latency analog input clock input data output t do t ad t cl t ch figure 6. system and output timing diagram system timing requirements figure 6 shows the relationship between the clock input, analog input, and data output. the max1444 samples at the falling edge of the input clock. output data is valid on the rising edge of the input clock. the output data has an internal latency of 5.5 clock cycles. figure 5 shows the relationship between the input clock parameters and the valid output data. __________applications information figure 7 shows a typical application circuit containing a single-ended to differential converter. the internal refer- ence provides a v dd /2 output voltage for level shifting purposes. the input is buffered and then split to a volt- age follower and inverter. a lowpass filter follows the op amps to suppress some of the wideband noise associ- ated with high-speed op amps. the user may select the r iso and c in values to optimize the filter performance to suit a particular application. for the application in figure 7, an r iso of 50 ? is placed before the capaci- tive load to prevent ringing and oscillation. the 22pf c in capacitor acts as a small bypassing capacitor. using transformer coupling an rf transformer (figure 8) provides an excellent solution for converting a single-ended source signal to a fully differential signal, required by the max1444 for optimum performance. connecting the transformer? center tap to com provides a v dd /2 dc level shift to the input. although a 1:1 transformer is shown, a step- up transformer may be selected to reduce the drive requirements. a reduced signal swing from the input driver, such as an op amp, may also improve the over- all distortion. in general, the max1444 provides better sfdr and thd with fully differential input signals than single- ended drive, especially for very high input frequencies. in differential input mode, even-order harmonics are lower since both inputs (in+, in-) are balanced, and each of the inputs only requires half the signal swing compared to single-ended mode. single-ended ac-coupled input signal figure 9 shows an ac-coupled, single-ended applica- tion. the max4108 op amp provides high speed, high bandwidth, low noise, and low distortion to maintain the integrity of the input signal.
max1444 10-bit, 40msps, 3.0v, low-power adc with internal reference ______________________________________________________________________________________ 15 max1444 t1 n.c. v in 4 3 2 5 6 1 10pf 10pf 0.1 f 0.1 f 2.2 f 25 ? 25 ? mini-circuits adt1?wt in- in+ com figure 8. using a transformer for ac coupling max1444 0.1 f 1k ? 1k ? 100 ? 100 ? c in com c in in+ in- 0.1 f r iso r iso refp refn r iso = 50 ? c in = 22pf v in max4108 figure 9. single-ended ac-coupled input input 300 ? -5v 5v 0.1 f 0.1 f 0.1 f c in 22pf c in 22pf r iso 50 ? r iso 50 ? -5v 600 ? 300 ? 300 ? in+ in- lowpass filter com 600 ? 5v -5v 0.1 f 600 ? 300 ? 600 ? 300 ? 0.1 f 0.1 f 0.1 f 5v 0.1 f 300 ? max4108 max1444 max4108 max4108 lowpass filter figure 7. typical application circuit for single-ended to differential conversion
max1444 10-bit, 40msps, 3.0v, low-power adc with internal reference 16 ______________________________________________________________________________________ buffered external reference drives multiple adcs multiple-converter systems based on the max1195 are well suited for use with a common reference voltage. the refin pin of those converters can be connected directly to an external reference source. a precision bandgap reference like the max6062 generates an external dc level of 2.048v (figure 10), and exhibits a noise voltage density of 150nv/ hz . its output passes through a one-pole lowpass filter (with 10hz cutoff fre- quency) to the max4250, which buffers the reference before its output is applied to a second 10hz lowpass filter. the max4250 provides a low offset voltage (for high gain accuracy) and a low noise level. the passive 10hz filter following the buffer attenuates noise pro- duced in the voltage reference and buffer stages. this filtered noise density, which decreases for higher fre- quencies, meets the noise levels specified for precision adc operation. refout 29 n.c. refin 31 refp 32 refn 1 com 2 0.1 f 0.1 f 0.1 f 0.1 f 2.048v 100 f 2 5 3 2 3 1 4 1 max1444 n = 1 max4250 refout 29 n.c. refin 31 refp 32 refn 1 com 2 0.1 f 0.1 f 0.1 f 0.1 f max1444 n = 1000 0.1 f 162 ? 16.2k ? 3.3v 1 f 10hz lowpass filter 10hz lowpass filter note: one front-end reference circuit design may be used with up to 1000 adcs. 2.2 f 10v 0.1 f 0.1 f 3.3v max6062 figure 10. buffered external reference drives up to 1000 adcs
max1444 10-bit, 40msps, 3.0v, low-power adc with internal reference ______________________________________________________________________________________ 17 unbuffered external reference drives multiple adcs connecting each refin to analog ground disables the internal reference of each device, allowing the internal reference ladders to be driven directly by a set of exter- nal reference sources. followed by a 10hz lowpass fil- ter and precision voltage-divider (figure 11), the max6066 generates a dc level of 2.500v. the buffered outputs of this divider are set to 2.0v, 1.5v, and 1.0v, with an accuracy that depends on the tolerance of the divider resistors. the three voltages are buffered by the max4252, which provides low noise and low dc offset. the individual voltage followers are connected to 10hz lowpass filters, which filter both the reference voltage and amplifier noise to a level of 3nv/ hz . the 2.0v and 1.0v reference voltages set the differential full-scale range of the associated adcs at 2v p-p . the 2.0v and 1.0v buffers drive the adc? internal ladder resistances between them. note that the common power supply for all active components removes any concern regarding refout 29 n.c. refin 31 refp 32 refn 1 com 2 0.1 f 0.1 f 0.1 f 330 f 6v 330 f 6v 330 f 6v 10 f 6v 11 4 3 2 3 1 2 1 max1444 n = 1 max6066 1/4 max4252 refout 29 n.c. refin 31 refp 32 refn 1 com 2 0.1 f 0.1 f 0.1 f max1444 n = 32 47 ? 2.0v at 8ma 1.47k ? 21.5k ? 3.3v 1 f 21.5k ? 21.5k ? 21.5k ? 21.5k ? note: one front-end reference circuit design may be used with up to 32 adcs. 2.2 f 10v 0.1 f 0.1 f 3.3v 2.0v 10 f 6v 11 4 5 6 7 1/4 max4252 47 ? 1.5v at 0ma 1.47k ? 3.3v 10 f 6v 11 4 10 9 8 1/4 max4252 47 ? 1.0v at -8ma 1.47k ? 3.3v 3.3v max4254 power-supply bypassing. place capacitor as close as possible to the op amp. 0.1 f 1.5v 1.0v figure 11. unbuffered external reference drives up to 32 adcs
max1444 10-bit, 40msps, 3.0v, low-power adc with internal reference 18 ______________________________________________________________________________________ power-supply sequencing when powering up or down. with the outputs of the max4252 matching better than 0.1%, the buffers and subsequent lowpass filters can be replicated to support as many as 32 adcs. for applications that require more than 32 matched adcs, a voltage reference and divider string common to all converters is highly recommended. grounding, bypassing, and board layout the max1444 requires high-speed board layout design techniques. locate all bypass capacitors as close to the device as possible, preferably on the same side as the adc, using surface-mount devices for minimum inductance. bypass v dd , refp, refn, and com with two parallel 0.1? ceramic capacitors and a 2.2? bipolar capacitor to gnd. follow the same rules to bypass the digital supply (ov dd ) to ognd. multilayer boards with separated ground and power planes pro- duce the highest level of signal integrity. consider using a split ground plane arranged to match the physi- cal location of the analog ground (gnd) and the digital output driver ground (ognd) on the adc's package. the two ground planes should be joined at a single point so that the noisy digital ground currents do not interfere with the analog ground plane. the ideal loca- tion of this connection can be determined experimen- tally at a point along the gap between the two ground planes that produces optimum results. make this con- nection with a low-value, surface-mount resistor (1 ? to 5 ? ), a ferrite bead, or a direct short. alternatively, all ground pins could share the same ground plane if the ground plane is sufficiently isolated from any noisy, dig- ital systems ground plane (e.g., downstream output buffer or dsp ground plane). route high-speed digital signal traces away from sensitive analog traces. keep all signal lines short and free of 90 turns. static parameter definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function once offset and gain errors have been nullified. the max1444? static linearity parameters are measured using the best straight-line fit method. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1lsb. a dnl error specification of less than 1lsb guarantees no missing codes and a monotonic transfer function. dynamic parameter definitions aperture jitter figure 12 depicts the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. aperture delay aperture delay (t ad ) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (figure 12). signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum a/d noise is caused by quantization error only and results directly from the adc? resolution (n bits): snr (max) = (6.02 x n + 1.76)db in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five har- monics, and the dc offset. hold analog input sampled data (t/h) t/h t ad t aj track track clk figure 12. t/h aperture timing
max1444 10-bit, 40msps, 3.0v, low-power adc with internal reference ______________________________________________________________________________________ 19 clk in+ control 10 adc ref system + bias output drivers d e c ref refin refout refp com refn oe v dd gnd ov dd ognd d9?0 in- pd t/h max1444 functional diagram signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to all spectral components minus the fundamental and the dc offset. effective number of bits (enob) enob specifies the dynamic performance of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quantization noise only. enob is computed from: total harmonic distortion (thd) thd is typically the ratio of the rms sum of the input signal? first four harmonics to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range (sfdr) sfdr is the ratio expressed in decibels of the rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next largest spurious component, excluding dc offset. intermodulation distortion (imd) the two-tone imd is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) inter- modulation products. the individual input tone levels are at -6.5db full scale. chip information transistor count: 5684 process: cmos thd vvvv v = +++ ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 1 log enob sinad = () ? 176 602 . .
max1444 10-bit, 40msps, 3.0v, low-power adc with internal reference maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. 32l tqfp, 5x5x01.0.eps package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)

▲Up To Search▲

Price & Availability of MAX1444EHJT

	To Download MAX1444EHJT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .